# Figure j = V*cf j + Vfn j (2)

Figure 2 Dual-Output Four-Leg Inverter

This inverter operates with two modes of operation: Different Frequency mode in which output frequencies can be different from each other and Equal Frequency mode in which output frequencies should be equal. The carrier-based pulse width modulation scheme of the dual output converter is developed and explained in 7. The converter operates in equal frequency mode (EF mode). Owing to which system becomes advantageous with dc bus voltage utilization becomes higher, device ratings become lower and it dissipates less switching power.

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First two offset voltages are calculated by using phase voltage commands of the two outputs as the fourth leg modulation signals shown in (1):

Vfnj = (–Vmax j/2) Vmin j > 0,

Vfnj = (–Vmin j / 2) Vmax j > 0,

Vfnj = – (Vmax j + Vmim j) / 2, otherwise                         (1)

Where, j = U or L, Vmax and Vmin are the instant maximum & minimum values of each of the upper & lower output phase voltages.

The next step would be finding the pole voltage commands (Vin, i= (a, b & c)) by adding the acquired offsets to the phase voltage commands

V*an j = V*af j + Vfn j

V*bn j = V*bf j + Vfn j

V*cn j = V*cf j + Vfn j                                                                                   (2)

Where, j = U or L

The pole voltage commands will work as the modulation signals of the remaining three legs. Now, offsets should be added to each of these sets therefore the upper and lower output modulation signals are shifted up and down respectively by doing this we can avoid their interference. According to the inverter operation mode, these offsets are determined; equation (3) is used for EF mode:

OffsetU = 1 – MU

OffsetL = ML – 1                                                             (3)

Where, j = U or L

The use of DF operation gives outputs of limited indices for two outputs. Which has many disadvantages like in reduced dc bus voltage utilization and this reduced dc bus voltage utilization gives increased dc bus voltage level. Inversely, in EF mode, the phase difference between the output voltages, is the only factor, that restricts the modulation indices. Equation (4) computes this limitation and illustrates the principal condition that should be maintained during the converter operation in EF modes:

MLsin(?Lt + ?L) + Vfn L + OffsetL

? MUsin(?Ut + ?U) + Vfn U + OffsetU                           (4)

The use of an additional neutral leg generates the main feature of three-phase inverter with, it is ability to deal with load unbalance in a standalone power supply system. The objective of the three-phase four leg inverter is to maintain desired sinusoidal output voltage waveform under overall

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